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? semiconductor components industries, llc, 2013 october, 2013 ? rev. 0 1 publication order number: ncv7351/d ncv7351 high speed can transceiver the ncv7351 can transceiver is the interface between a controller area network (can) protocol controller and the physical bus and may be used in both 12 v and 24 v systems. the transceiver provides differential transmit capability to the bus and differential receive capability to the can controller. the ncv7351 is an addition to the can high?speed transceiver family complementing ncv734x can stand?alone transceivers and previous generations such as amis42665, amis3066x, etc. due to the wide common?mode voltage range of the receiver inputs and other design features, the ncv7351 is able to reach outstanding levels of electromagnetic susceptibility (ems). similarly, extremely low electromagnetic emission (eme) is achieved by the excellent matching of the output signals. key features general ? compatible with the iso 11898?2 standard ? high speed (up to 1 mbps) ? v io pin on ncv7351d13 version allowing direct interfacing with 3 v to 5 v microcontrollers ? en pin on ncv7351d1e version allowing switching the transceiver to a very low current off mode ? excellent electromagnetic susceptibility (ems) level over full frequency range. very low electromagnetic emissions (eme) low eme also without common mode (cm) choke ? bus pins protected against >15 kv system esd pulses ? transmit data (txd) dominant t ime?out function ? under all supply conditions the chip behaves predictably. no disturbance of the bus lines with an unpowered node ? bus pins short circuit proof to supply voltage and ground ? bus pins protected against transients in an automotive environment ? thermal protection ? these are pb?free devices quality ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable typical applications ? automotive ? industrial networks http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information pin assignment marking diagram 1 8 soic?8 case 751az nv7351? = specific device code y = 3, 0, or e a = assembly location l = wafer lot y = year w = work week = pb?free package nv7351?y alyw 1 8 NCV7351D13R2G (top view) 5 6 7 8 1 2 3 4 txd rxd s gnd canl v cc v io canh ncv7351?3 ncv7351d10r2g (top view) 5 6 7 8 1 2 3 4 txd rxd s gnd canl v cc canh ncv7351?0 ncv7351d1er2g (top view) 5 6 7 8 1 2 3 4 txd rxd s gnd canl v cc canh ncv7351?e nc en
ncv7351 http://onsemi.com 2 table 1. key technical characteristics and operating ranges symbol parameter conditions min max unit v cc power supply voltage 4.5 5.5 v v uv undervoltage detection voltage on pin v cc 3.5 4.5 v v canh dc voltage at pin canh 0 < v cc < 5.5 v; no time limit ?50 +50 v v canl dc voltage at pin canl 0 < v cc < 5.5 v; no time limit ?50 +50 v v canh,l dc voltage between canh and canl pin 0 < v cc < 5.5 v ?50 +50 v v canh,lmax dc voltage at pin canh and canl during load dump condition 0 < v cc < 5.5 v, less than one second ? +58 v v esd electrostatic discharge voltage iec 61000?4?2 at pins canh and canl ?15 15 kv v o(dif)(bus_dom) differential bus output voltage in dominant state 45 < r lt < 65 1.5 3 v cm?range input common?mode range for comparator guaranteed differential receiver thresh- old and leakage current ?30 +35 v i cc supply current dominant; v txd = 0 v recessive; v txd = v cc ? 2.5 72 7.5 ma i ccs supply current in silent mode 1.4 3.5 ma t pd propagation delay txd to rxd see figure 5 90 245 ns t j junction temperature ?40 150 c
ncv7351 http://onsemi.com 3 block diagram mode control ncv7351 s gnd rxd 2 3 7 6 comp 5 timer txd 1 driver control thermal shutdown 8 4 canh canl en(1) 5 rb20120107 figure 1. block diagram of ncv7351 v cc v io /nc v io (1) only present in the ncv7351d1er2g (2) connected to v cc on versions without v io pin table 2. ncv7351: pin function description pin number pin name pin type pin function 1 txd digital input, internal pull?up transmit data input; low input dominant driver 2 gnd ground ground 3 v cc supply supply voltage 4 rxd digital output receive data output; dominant bus low output 5 nc not connected not connected, ncv7351?0 version only v io supply supply voltage for digital inputs/outputs, ncv7351?3 version only en digital input, internal pull?down enable control input, ncv7351?e version only 6 canl high voltage input/output low?level can bus line (low in dominant mode) 7 canh high voltage input/output high?level can bus line (high in dominant mode) 8 s digital input, internal pull?down silent mode control input
ncv7351 http://onsemi.com 4 application information ncv7351 s rxd txd 1 4 micro controller gnd vbat 5 v?reg gnd 2 5 8 canh canl 3 6 7 can bus . 3 v?reg rb20120808 figure 2. ncv7351?3 application diagram r lt = 60 r lt = 60 v cc v io ncv7351 s rxd txd 1 4 micro controller gnd vbat 5 v?reg gnd 2 5 8 canh canl 3 6 7 can bus . en rb20120808 figure 3. ncv7351?e application diagram v cc r lt = 60 r lt = 60
ncv7351 http://onsemi.com 5 functional description ncv7351 has three versions which differ from each other only by function of pin 5. (see also table 2) ncv7351?3 : pin 5 is v io pin, which is supply pin for transceiver digital inputs/output (supplying pins txd, rxd, s, en). the v io pin should be connected to microcontroller supply pin. by using v io supply pin shared with microcontroller the i/o levels between microcontroller and transceiver are properly adjusted. this allows in applications with microcontroller supply down to 3 v to easy communicate with the transceiver. (see figure 2) ncv7351?0 : pin 5 is not connected. this version is full replacement of the previous generation can transceiver amis30660. ncv7351?e : pin 5 is digital enable pin which allows transceiver to be switched off with very low supply current. operating modes the ncv7351 modes of operation are provided as illustrated in table 3. these modes are selectable through pin s and also en in case of ncv7351?e. table 3. operating modes mode pin s pin en (note 1) pin txd canh,l pins rxd normal 0 1 0 dominant 0 0 1 1 recessive 1 silent 1 1 x recessive 1 1 1 x dominant (note 3) 0 off (note 1) x 0 x floating floating 1. only applicable to ncv7351?e 2. ?x? = don?t care 3. can bus driven to dominant by another transceiver on the bus normal mode in the normal mode, the transceiver is able to communicate via the bus lines. the signals are transmitted and received to the can controller via the pins txd and rxd. the slopes on the bus lines outputs are optimized to give low eme. silent mode in the silent mode, the transmitter is disabled. the bus pins are in recessive state independent of txd input. t ransceiver listens to the bus and provides data to controller, but controller is prevented from sending any data to the bus. off mode in off mode, complete transceiver is disabled and consumes very low current. the can pins are floating not loading the can bus. over?temperature detection a thermal protection circuit protects the ic from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 180 c. because the transmitter dissipates most of the power, the power dissipation and temperature of the ic is reduced. all other ic functions continue to operate. the transmitter of f?state resets when the temperature decreases below the shutdown threshold and pin txd goes high. the thermal protection circuit is particularly needed in case of the bus line short circuits. txd dominant time?out function a txd dominant time?out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if pin txd is forced permanently low by a hardware and/or software application failure. the timer is triggered by a negative edge on pin txd. if the duration of the low?level on pin txd exceeds the internal timer value t dom , the transmitter is disabled, driving the bus into a recessive state. the timer is reset by a positive edge on pin txd. this txd dominant time?out time (t dom(txd) ) defines the minimum possible bit rate to 12 kbps. fail safe features a current?limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. the pins canh and canl are protected from automotive electrical transients (according to iso 7637; figure 4). internally, pin txd is pulled high, pin en and s low should the input become disconnected. pins txd, s, en and rxd will be floating, preventing reverse supply should the v cc supply be removed.
ncv7351 http://onsemi.com 6 definitions : all voltages are referenced to gnd (pin 2). positive currents flow into the ic. sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. table 4. absolute maximum ratings symbol parameter conditions min max unit v sup supply voltage v cc ?0.3 +6 v v canh dc voltage at pin canh 0 < v cc < 5.5 v; no time limit ?50 +50 v v canl dc voltage at pin canl 0 < v cc < 5.5 v; no time limit ?50 +50 v v ios dc voltage at pin txd, rxd, s, en, v io notes 4 and 5 ?0.3 6 v v esd electrostatic discharge voltage at all pins according to eia?jesd22 note 6 ?6 6 kv electrostatic discharge voltage at canh,canl, pins according to eia?jesd22 note 6 ?8 8 kv electrostatic discharge voltage at canh , canl pins according to iec 61000?4?2 note 7 ?15 15 kv standardized charged device model esd pulses according to esd?stm5.3.1?1999 750 75 0 v v schaff transient voltage at canh, canl pins, see figure 4 note 8 ?150 100 v latch?up static latch?up at all pins note 9 150 ma t stg storage temperature ?55 +150 c t j maximum junction temperature ?40 +170 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. en pin only available on ncv7351?e version 5. v io pin only available on ncv7351?3 version 6. standardized human body model electrostatic discharge (esd) pulses in accordance to eia?jesd22. equivalent to discharging a 1 00 pf capacitor through a 1.5 k resistor. 7. system human body model electrostatic discharge (esd) pulses. equivalent to discharging a 150 pf capacitor through a 330 resistor referenced to gnd. verified by external test house 8. pulses 1, 2a,3a and 3b according to iso 7637 part 3. results were verified by external test house. 9. static latch?up immunity: static latch?up protection level when tested according to eia/jesd78. table 5. thermal characteristics symbol parameter conditions value unit r ja_1 thermal resistance junction?to?air, 1s0p pcb (note 10) free air 125 k/w r ja_2 thermal resistance junction?to?air, 2s2p pcb (note 11) free air 75 k/w 10. test board according to eia/jedec standard jesd51?3, signal layer with 10% trace coverage. 11. test board according to eia/jedec standard jesd51?7, signal layers with 10% trace coverage.
ncv7351 http://onsemi.com 7 electrical characteristics v cc = 4.5 v to 5.5 v; v io = 2.8 v to 5.5 v; t j = ?40 c to +150 c; r lt = 60 unless specified otherwise. on chip versions without v io pin reference voltage for all digital inputs and outputs is v cc instead of v io . table 6. characteristics symbol parameter conditions min typ max unit supply (pin v cc ) i cc supply current in normal mode dominant; v txd = 0 v recessive; v txd = v io ? 2.5 50 4.6 72 7.5 ma i ccs supply current in silent mode 1.4 2.3 3.5 ma i ccoff supply current in off mode on ncv7351?e version only ? 7 18 a i ccoff supply current in off mode ncv7351?e version only t j 100 c, note 13 ? 7 10 a v uvdvcc undervoltage detection voltage on v cc pin 3.5 4 4.5 v supply (pin v io ) on ncv7351?3 version only v iorange supply voltage range on pin v io 2.8 ? 5.5 v i io supply current on pin v io normal mode dominant; v txd = 0 v recessive; v txd = v io 100 50 240 125 500 265 a i ios supply current on pin v io silent mode bus is recessive; v txd = v io ? 2 16 a v uvdvio undervoltage detection voltage on v io pin 2.1 2.4 2.7 v transmitter data input (pin txd) v ih high?level input voltage , on ncv7351?3 version only output recessive 0.7 x v io ? v io + 0.3 v v ih high?level input voltage, on ncv7351?1 and ncv7351?e versions only output recessive 2.7 ? v cc + 0.3 v v il low?level input voltage output dominant ?0.3 ? +0.3 x v io v r txd txd pin pull up 22 30 50 k c i input capacitance note 13 ? 5 10 pf transmitter mode select (pin s and en) v ih high?level input voltage, on ncv7351?3 version only silent mode 0.7 x v io ? v io + 0.3 v v ih high?level input voltage on ncv7351?1 and ncv7351?e versions only silent or enable mode 2.7 ? v cc + 0.3 v v il low?level input voltage normal mode ?0.3 ? 0.3 x v io v r s,en s and en pin pull down note 12 0.55 1.1 1.5 m c i input capacitance note 13 ? 5 10 pf receiver data output (pin rxd) i oh high?level output current normal mode v rxd = v io ? 0.4 v ?1 ?0.4 ?0.1 ma i ol low?level output current v rxd = 0.4 v 1.5 6 11 ma bus lines (pins canh and canl) 12. en pin only available on ncv7351?e version 13. not tested in production. guaranteed by design and prototype evaluation.
ncv7351 http://onsemi.com 8 table 6. characteristics symbol unit max typ min conditions parameter bus lines (pins canh and canl) v o(reces) (norm) recessive bus voltage on pins canh and canl v txd = v io ; no load normal mode 2.0 2.5 3.0 v i o(reces) (canh) recessive output current at pin canh ?30 v < v canh < +35 v; 0 v < v cc < 5.5 v ?2.5 ? +2.5 ma i o(reces) (canl) recessive output current at pin canl ?30 v < v canl < +35 v; 0 v < v cc < 5.5 v ?2.5 ? +2.5 ma i li(canh) input leakage current to pin canh 0 < r(v cc to gnd) < 1 m v canl = v canh = 5 v ?10 0 10 a i li(canl) input leakage current to pin canl ?10 0 10 a v o(dom) (canh) dominant output voltage at pin canh v txd = 0 v; v cc = 4.75 v to 5.25 v 3.0 3.6 4.25 v v o(dom) (canl) dominant output voltage at pin canl v txd = 0 v; v cc = 4.75 v to 5.25 v 0.5 1.4 1.75 v v o(dif) (bus_dom) differential bus output voltage (v canh ? v canl ) v txd = 0 v; dominant; v cc = 4.75 v to 5.25 v 45 < r lt < 65 1.5 2.25 3.0 v v o(dif) (bus_rec) differential bus output voltage (v canh ? v canl ) v txd = v io ; recessive; no load ?120 0 +50 mv v o(sym) (bus_dom) bus output voltage symmetry v canh + v canl v txd = 0 v v cc = 4.75 v to 5.25 v 0.9 ? 1.1 v cc i o(sc) (canh) short circuit output current at pin canh v canh = 0 v; v txd = 0 v ?90 ?70 ?40 ma i o(sc) (canl) short circuit output current at pin canl v canl = 36 v; v txd = 0 v 40 70 100 ma v i(dif) (th) differential receiver threshold voltage ?12 v < v canl < +12 v; ?12 v < v canh < +12 v; 0.5 0.7 0.9 v v ihcm(dif) (th) differential receiver threshold voltage for high common?mode ?30 v < v canl < +35 v; ?30 v < v canh < +35 v; 0.40 0.7 1.0 v r i(cm) (canh) common?mode input resistance at pin canh 15 26 37 k r i(cm) (canl) common?mode input resistance at pin canl 15 26 37 k r i(cm) (m) matching between pin canh and pin canl common mode input resistance v canh = v canl ?0.8 0 +0.8 % r i(dif) differential input resistance 25 50 75 k c i(canh) input capacitance at pin canh v txd = v io ; not tested ? 7.5 20 pf c i(canl) input capacitance at pin canl v txd = v io ; not tested ? 7.5 20 pf c i(dif) differential input capacitance v txd = v io ; not tested ? 3.75 10 pf thermal shutdown t j(sd) shutdown junction temperature junction temperature rising 160 180 200 c timing characteristics (see figures 5 and 6) t d(txd?buson) delay txd to bus active c i = 100 pf between canh to canl ? 75 ? ns t d(txd?busoff) delay txd to bus inactive c i = 100 pf between canh to canl ? 65 ? ns t d(buson?rxd) delay bus active to rxd c rxd = 15 pf ? 70 ? ns t d(busoff?rxd) delay bus inactive to rxd c rxd = 15 pf ? 7 0 ? ns t pd propagation delay txd to rxd (both edges) c i = 100 pf between canh to canl 90 14 0 245 ns t dom(txd) txd dominant time for time?out v txd = 0 v 1.5 2.5 5 ms 12. en pin only available on ncv7351?e version 13. not tested in production. guaranteed by design and prototype evaluation.
ncv7351 http://onsemi.com 9 measurement setups and definitions ncv7351 gnd 2 3 canh canl 5 6 7 s 8 rxd 4 txd 1 1 nf 100 nf +5 v 15 pf 1 nf transient generator rb20120808 figure 4. test circuit for automotive transients v cc v io /en 8 ncv7351 gnd 2 3 canh canl 5 6 7 s rxd 4 txd 1 100 nf + 5 v 15 pf 47 uf 100 pf r l rb20120808 8 figure 5. test circuit for timing characteristics v cc v io /en
ncv7351 http://onsemi.com 10 dominant 0.9 v 0.5 v recessive 50% recessive 50% txd canh canl rxd rb20130429 figure 6. transceiver timing diagram (1) on ncv7351?3 v cc is replaced by v io t d(txdbuson) t d(busoff?rxd) 0.7 x v cc (1) t d(buson?rxd) t d(txdbusoff) 0.3 x v cc (1) v i(dif) = v canh ? v canl t pd t pd device ordering information part number description temperature range package shipping ? NCV7351D13R2G high speed can transceiver with v io pin ?40 c to +125 c soic 150 8 green (matte sn, jedec ms?012) (pb?free) 3000 / tape & reel ncv7351d10r2g high speed can transceiver with pin 5 nc ncv7351d1er2g high speed can transceiver with en pin ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7351 http://onsemi.com 11 package dimensions soic 8 case 751az issue o
ncv7351 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv7351/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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